Newer types of substrates can be used as replacements for traditional silicon wafers to improve silicon-based electronic device performance. For example, wafers that have a silicon-germanium (SiGe) alloy layer can provide improved channel-layer performance in a strained-silicon layer grown on a relaxed, i.e., relatively strain-free, SiGe layer. Strained silicon can provide improved minority carrier mobility for a surface-channel layer in, for example, metal-oxide-semiconductor (MOS) field-effect transistors (FET).
The carrier mobility of the silicon channel layer generally increases with the level of strain in the layer. The level of strain is determined by the lattice mismatch with the underlying relaxed SiGe layer. The lattice mismatch, in turn, is determined by the Ge concentration of the relaxed SiGe layer. That is, the lattice spacing of a relaxed SiGe layer generally increases with increasing Ge concentration.
Thus, as the Ge concentration in a relaxed SiGe substrate layer is increased, the electron mobility in the overlying strained-silicon channel layer generally increases. The electron mobility generally saturates beyond a Ge concentration of approximately 20 atomic %, but the hole mobility continues to increase as the Ge concentration rises.
The behavior of electron and hole mobility is of particular significance, for example, in the performance of an inverter, one of the basic building blocks of integrated circuit devices. An inverter includes both an NMOS (i.e., n-channel) and PMOS (i.e., p-channel) transistor, and the inverter delay is dependent upon both the NMOS and PMOS transistor drive currents. With mobility enhancements of the electron and hole charge carriers, the drive current increases, and the inverter stage delay decreases.
An inverter delay is a function of both the NMOS and PMOS device transconductance. The delay can be described as:       t    p    ≈                    C        L            2        ⁢          (                        1                      K            P                          +                  1                      K            n                              )      where Ki=CvsatCoxWi, “i” represents p or n, and tp is the total inverter delay time. The delay is related to the ability of the NMOS and PMOS transistors to drive the inverter capacitance, CL. Kp and Kn are, respectively, related to the transconductance of the PMOS and NMOS transistors. C is a constant, Vsat is the saturation velocity of the carrier in the channel, Cox is the gate capacitance per unit area, and Wi is the width of the corresponding NMOS or PMOS transistor (i.e., the width of the gate).
The NMOS and PMOS transistors of a conventional Si inverter can be designed to provide approximately equal driving capabilities by appropriately adjusting the widths of the devices. In this case, the following expression aids in an estimate of improvement in inverter performance:             t      p        ≈                  B        2            ⁢              (                              1                                          e                p                            ⁢                              ω                p                                              +                      1                                          e                n                            ⁢                              ω                n                                                    )              ,where B is a constant, ep is the enhancement factor in PMOS drive current due to channel improvement relative to a standard silicon component (e.g., through use of strained-silicon), en is the enhancement factor in NMOS drive current, ωp is any relative width change in the PMOS transistor (new width divided by the width of standard a standard silicon PMOS component in a reference standard inverter), and ωn is any relative width change in the NMOS transistor. This expression is an approximation because any large change in device width can affect the constant B, which is associated with the overall inverter capacitance.
A standard Si inverter is typically optimized to minimize stage delay by widening the PMOS transistor in order to balance the current drive in the NMOS and PMOS transistors. This requirement arises because standard silicon devices have a much higher NMOS drive current than PMOS drive current (due to electrons having a much higher mobility than holes in unstrained silicon).
Strained silicon with 20 atomic % Ge on a relaxed SiGe substrate can increase electron mobility by approximately 80%, with a hole mobility at best only slightly enhanced. Thus, strained silicon can cause an increase in mobility mismatch, and, therefore, an increase in drive current mismatch between the NMOS and PMOS transistors in the inverter. Therefore, the inverter stage delay generally does not decrease by a full 80% when strained silicon is employed as a channel layer.
As the germanium concentration in a relaxed SiGe substrate rises to 30% and to 40%, the hole mobility increases, respectively, by approximately 40% and over 100%. Beyond a concentration of 40%, little or no further enhancement of the hole mobility occurs. At 40% Ge in the relaxed SiGe substrate, the ratio of the drive currents in the NMOS and PMOS transistors generally is nearly the same ratio as in a standard device.
Thus, asymmetrical mobilities and transistor sizes remain a problem for inverters and other semiconductor devices.